1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching layers of polysilicon on a mixed-mode processing environment. The method provides for the removal of poly-2 residue from sidewalls of a poly-1 pattern while device Isat performance and mixed-mode product yield are improved.
2. Description of the Prior Art
The fabrication of semiconductor devices requires the application of numerous interdependent technical disciplines which are collectively applied in a high-speed, cost-competitive semiconductor manufacturing facility.
To enhance the competitive nature of creating semiconductor devices and to further enhance the performance characteristics of these devices, a number of semiconductor devices are of a mixed-mode design in which both analog and digital circuits are created on the same chip.
Device performance is further improved by increasing device density, since this approach reduces the interconnect and the distance between other functional elements of the device while at the same time allowing for the creation of a larger number of active devices in or on the surface of one substrate.
It is obvious that device yield is a critical parameter in creating semiconductor devices since device yield is directly related to the cost of the created devices. From this is it obvious that a continuous effort is made to increase the device yield while at the same time maintaining or improving device performance characteristics.
More specifically, in the creation of 0.35 μm mixed mode semiconductor devices, two overlying layers of polysilicon are frequently used for as an example the creation of flash memory EEPROM devices, which use a double poly structure whereby the upper poly forms the control gate and the word lines of the structure while the lower poly is the floating gate. In a typical structure, the control-gate poly overlaps the channel region that is adjacent to the channel under the floating gate. The extension of the control gate over the channel region is referred to as the series enhancement-mode transistor and is required because when the cell is erased, a positive charge remains on the floating gate inverting the channel under floating gate. The series enhancement-mode transistor prevents the flow of current from the source to the drain regions of the MOS device.
Device performance improvements are typically achieved by reducing device dimensions, which further enables increased packaging density of the created semiconductor devices. It is therefore desirable to create memory devices over smaller surface regions of the substrate. One of the frequently applied methods for the creation of etched layers of poly, that are part of a split gate flash memory device, is the use of a hardmask layer that overlies a layer of poly that needs to be etched.
The invention address concerns and aspects of creating stacked or overlying layers of polysilicon and, more specifically, concerns of poly-2 residue over sidewalls of patterned underlying poly-1.
U.S. Pat. No. 6,165,375 (Yang et al.) claims a flash step in an etch process.
U.S. Pat. No. 6,165,861 (Liu et al.) shows a method for a mixed mode product.
U.S. Pat. No. 6,103,622 (Huang) and U.S. Pat. No. 6,103,621 (Huang) show processes for mixed mode products using poly etches.